1. Field Of The Invention
The present invention relates to semiconductor memories, and more particularly, to a high speed, low power, word line driver circuit.
2. Description Of The Prior Art
In a semiconductor memory array with (2.sup.n) word lines, an address input of (n) bits is required to select one of the word lines. Each word line in the array includes a decoder circuit and a driver circuit. All of the decoder circuits receive and decipher the (n) bit address input, and in response thereto, one word line in the array is selected. The driver circuit of the selected word line drives the selected word line, thus allowing a memory cell or cells on the selected word line to be accessed. All the other word lines in the array are deselected.
For certain applications such as cache memory on a microprocessor chip, fast memory cycle times and low power consumption are desired. A memory cycle is the time between successive operations, i.e., a read or write. The rise time, recovery time, and power consumption of a driver circuit are all critical to the overall performance of the memory.
A prior an word line driver circuit is described in the article entitled "An Experimental Soft-Error Immune 64-Kb 3ns Bipolar Ram", Kunihiko Yamaguchi et al., IEEE Bipolar Circuits and Technology Meeting, 1988. This article describes a two-cascaded transistor driver circuit (FIG. 3) which pulls up a selected word line in response to a word line select signal. A first discharge circuit is coupled at an intermediate node between the two cascaded transistors. A second discharge circuit is coupled to the output node which drives the word line. Each discharge circuit includes a pair of cascaded transistors, a capacitor, and a pair of resistors. This driver circuit has several disadvantages. First, the two discharge circuits each include a constant current source which dissipates power, regardless of whether the word line is selected or deselected. Accordingly, the size of the memory array is limited for a given power budget. Second, the discharge circuit is active when the row is selected, which slows down the pull up time of the driver. Third, the capacitor and resistors of each discharge circuit create an RC constant which determines the time period in which the discharge circuit remains on. This RC time constant may differ between wafer runs due to process variations. The discharge circuit is therefore process sensitive and very difficult to manufacture so that the timing of the discharge circuit coincides with that of the memory cycle.
Another prior art driver circuit is described in an article entitled "A 4-ns 4K.times.1-bit Two-Port BiCMOS SRAM", by Yang et al., IEEE Journal of Solid-State Circuits, Vol. No. 5, 1988. This article describes a two-stage Darlington driver circuit (FIG. 8) for each word line. A common pull down current source is coupled to the output of each driver circuit through a resistor. The shared current source reduces power consumption, but at the expense of the operational speed of the circuit. When all the word lines are deselected, the constant current source is equally shared among all the driver circuits. When a word line is selected, the selected driver circuit draws more current than the inactive drivers. The rise time of the selected word line is slowed because as the driver raises the word line, the driver must supply more current to the resistor, so less current is actually available to drive the word line. The recovery time of the selected word line is very slow because the pull down resistor and the word line capacitance creates an RC delay during pull down. Furthermore, if there is an overlap between a word line being selected and another word line being deselected, which is a common occurrence in a SRAM, the recovery time of the deselected word line is further increased because the newly selected word line driver "steals" away much of the current that the deselected word line driver would otherwise be using to pull down the newly deselected word line.
Yet another driver circuit is described in an article entitled "High Speed Low-Power Charge-Buffered Active Pull Down ECL Circuit", by C. T. Chuang et al., IEEE, 1991. This article describes a driver with an active pull down circuit (FIG. 1b). The driver is coupled between the NOR side of an ECL differential pair decoder and the word line. The active pull down circuit includes a capacitor coupled to the OR side of the ECL differential decoder and a pull down transistor. During word line recovery, the capacitor is discharged through the pull down transistor as current is switched through the OR side of the differential pair. As a result, the pull down transistor is turned on, providing an active pull down path between the word line and ground. In time, the charge on the capacitor discharges and the pull down transistor turns off. This active pull down circuit also has several disadvantages. Since the gain (beta) of the pull down transistor may vary from wafer run to wafer run during fabrication, it is difficult to determine the correct size of the capacitor. If the gain of the pull down transistor does not match the size of the capacitor, the pull down transistor may not turn on hard enough or may turn off very slowly, which needlessly consumes power. The capacitor also tends to be very large and occupies valuable space on the semiconductor die.